The disclosed embodiments of the present invention relate to a digital signal processing circuit for generating an output signal according to non-overlapping clock signals and input bit streams and related wireless communication transmitters.
Use of digital power amplifiers (DPAs) is desirable in some transmitters within wireless communication systems to enhance power efficiency, reduce the hardware cost and reduce the chip size. The conventional topologies of the digital radio-frequency (RF) transmitter front-end may include a digital polar transmitter and an I/Q RF digital-to-analog converter (DAC). In a condition where the digital polar transmitter and the I/Q RF DAC are both implemented using the same silicon area, the power efficiency of the digital polar transmitter is higher than that of the I/Q RF DAC. Please refer to FIG. 1 and FIG. 2. FIG. 1 is a diagram illustrating a simplified digital polar transmitter 100 having power amplifiers implemented in silicon areas A+ and A−. FIG. 2 is a diagram illustrating a simplified I/Q RF DAC 200 having power amplifiers implemented in two smaller silicon areas ½·A+ and two silicon areas ½·A−. Each of the digital polar transmitter 100 and the I/Q RF DAC 200 generates a differential output including a positive RF signal RF+ and a negative RF signal RF−. Regarding the conventional digital polar transmitter 100, power amplifiers implemented in the silicon area A+ generate the positive RF signal RF+ according to a phase modulation signal AM and an amplitude modulation signal PM, and power amplifiers implemented in the other silicon area A− generate the negative RF signal RF− according to the phase modulation signal AM and the amplitude modulation signal PM. The upmixing power P1 of positive RF signal RF+/negative RF signal RF− generated from the digital polar transmitter 100 may be expressed as follows.
                                                                        P                ⁢                                                                  ⁢                1                            =                            ⁢                                                α                  ·                                      ⅇ                                          j                      ⁢                                                                                          ⁢                                              ϕ                        ⁡                                                  (                          t                          )                                                                                                                    ×                                  β                  ·                                      ⅇ                                          j                      ⁢                                                                                          ⁢                                              ω                        LO                                            ⁢                      t                                                                                                                                              =                            ⁢                                                A                  ⁡                                      (                    t                    )                                                  ⁢                                  ⅇ                                      j                    ⁢                                                                                  ⁢                                          ϕ                      ⁡                                              (                        t                        )                                                                                            ×                                  4                  π                                ⁢                                  ⅇ                                      j                    ⁢                                                                                  ⁢                                          ω                      LO                                        ⁢                    t                                                                                                                          ≅                            ⁢                              1.27                ⁢                                  A                  ⁡                                      (                    t                    )                                                  ⁢                                  ⅇ                                      j                    ⁡                                          [                                                                                                    ω                            LO                                                    ⁢                          t                                                +                                                  ϕ                          ⁡                                                      (                            t                            )                                                                                              ]                                                                                                                              (        1        )            
In above equation (1), the parameter α depends on the silicon area in which the power amplifiers are disposed, and the parameter β depends on the coefficient of a first-order harmonic term of a periodic square wave signal involved in up-conversion. In this example, α=A(t) and
  β  =            4      π        .  
Regarding the conventional I/Q RF DAC 200, power amplifiers implemented in two silicon areas ½·A+ generate the positive RF signal RF+ according to an in-phase input I, a quadrature input Q, a local oscillator (LO) input LO_I with a duty cycle of 50%, and an LO input LO_Q with a duty cycle of 50%; besides, power amplifiers implemented in the other two silicon areas ½·A− generate the negative RF signal RF− according to the in-phase input I, the quadrature input Q, the LO input LO_I with the duty cycle of 50%, and the LO input LO_Q with the duty cycle of 50%. As the conventional I/Q RF DAC 200 employs LO inputs each having a duty cycle of 50%, the LO inputs are not non-overlapping clock signals. Thus, at any moment, some power amplifiers of the in-phase channel and some power amplifiers of the quadrature channel should be active simultaneously. As a result, the up-conversion of the in-phase input I and the up-conversion of the quadrature input Q cannot share the same power amplifier, and therefore require respective dedicated power amplifiers. As to the I/Q RF DAC 200, the aforementioned mention parameter α would become
      1          2        ·      A    ⁡          (      t      )      due to the smaller silicon area ½·A+/½·A−. Suppose that the LO input is implemented by the same periodic square wave signal having a first-order harmonic term with a coefficient of
      4    π    .Therefore, the upmixing power P2 of positive RF signal RF+/negative RF signal RF− generated from the conventional I/Q RF DAC 200 may be expressed as follows.
                              P          ⁢                                          ⁢          2                =                                                            1                                  2                                            ·                              A                ⁡                                  (                  t                  )                                                      ⁢                          ⅇ                              j                ⁢                                                                  ⁢                                  ϕ                  ⁡                                      (                    t                    )                                                                        ×                          4              π                        ⁢                          ⅇ                              j                ⁢                                                                  ⁢                                  ω                  LO                                ⁢                t                                              ≅                      0.9            ⁢                          A              ⁡                              (                t                )                                      ⁢                          ⅇ                              j                ⁡                                  [                                                                                    ω                        LO                                            ⁢                      t                                        +                                          ϕ                      ⁡                                              (                        t                        )                                                                              ]                                                                                        (        2        )            
As can be seen from above equations (1) and (2), the power efficiency of the digital polar transmitter 100 is twice as large as that of the I/Q RF DAC 200 when respective consumed silicon areas are the same. Thus, the I/Q RF DAC 200 requires more than double silicon area to deliver the same amount of power as the digital polar transmitter 100 counting the power loss due to overlapped quadrature signals. However, the I/Q RF DAC topology has certain advantages/benefits over the digital polar transmitter topology. For example, compared to the digital polar transmitter topology, the I/Q RF DAC topology has better signal integrity and lower signal bandwidth requirement, and can avoid the use of a high clock rate CORDIC (Coordinate Rotation Digital Computer) which consumes large chip area and digital power. Thus, there is a need for an innovative IQ processing-based transmitter design with improved power efficiency.